Wafer level chip size packaging (WLCSP) technique is a process in which a whole wafer is subjected to a packaging, followed by slicing the wafer into individual finished chips, and the packaged chip has a dimension identical to that of the die. WLCSP technique is completely different from conventional packaging techniques such as ceramic leadless chip carrier, organic leadless chip carrier and digital camera module, and satisfies the requirements for the microelectronic products with light weight, small dimension (especially in length and thickness) and low cost. A chip packaged by the WLCSP technique achieves a high level of miniaturization, and its cost decreases prominently with the decrease of chip size and the increase of wafer size. WLCSP technique can integrate IC design, wafer fabrication, packaging test and substrate fabrication, and is a hotspot and development trend in the packaging technological field.
Chinese Patent Application No. 200610096808.X discloses a double-layer lead packaging structure and a method for fabricating the same which is based on WLCSP technique. As shown in FIG. 1, the double-layer lead packaging structure comprises a glass substrate 105 having a cavity wall 110, a chip 120 having a light-sensing element 101 and a compatible pad 115, a glass layer 130, and a solder bump 150. A first surface of the chip 120 on which the light-sensing element 101 is provided connects with the cavity wall 110 through the compatible pad 115. An insulation layer 125 is sandwiched between a second surface of the chip 120 and a first surface of the glass layer 130. A second surface of the glass layer 130 is partially coated with a first solder mask layer 135. The surface of the first solder mask layer 135 is coated partially with a first metal layer 140. The sidewalls of the glass layer 130, the insulation layer 125 and the cavity wall 110 are coated partially with a second metal layer 141, and the second metal layer 141 connects with the compatible pad 115 and the first metal layer 140 to form an electrical connection. The surface of the first metal 140 which does not contact with the first solder mask layer 135 and the surface of the first solder mask layer 135 which does not contact with the glass layer 130 are coated with a second solder mask layer 145, and an opening is provided on the second solder mask layer 145 to expose the first metal layer 140. The inner surface of the opening is coated with the second metal layer 141 which connects with the first metal layer 140 electrically and extends to the second solder mask layer 145 at a position corresponding to the solder bump 150. A protective layer 146 is formed on the surface of the second metal layer 141, and an opening is formed in the protective layer 146 at a position corresponding to the solder bump 150 to expose the second metal layer 141. The solder bump 150 connects with the second metal layer 141 electrically through the opening.
However, other packaging structures suitable for various fabrication processes are still in need.